Method And System For Enabling Video Communication Via Ethernet Utilizing Asymmetrical Physical Layer Operations

ABSTRACT

Signals may be communicated between a video source and a video rendering device via and asymmetrical multi-rate Ethernet physical layer (PHY). The asymmetric multi-rate PHY may support multiple rates. The asymmetrical multi-rate Ethernet PHY may handle compressed and/or uncompressed, encrypted and/or unencrypted video signals and may handle audio/video bridging. One or more of the communicated signals may be modified by an echo cancellation operation, a near end cross talk (NEXT) cancellation operation, equalization, a far end cross talk (FEXT) cancellation operation and/or a forward error correction (FEC) operation. An aggregate communication rate may be evenly or unevenly distributed among one or more links coupling the video signal source to the video rendering device. A plurality of links coupling the video signal source to said video rendering device may also be aggregrated.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This application makes reference to and claims priority to United StatesProvisional Application Ser. No. 60917870 (Attorney Docket No.18598US01), filed on May 14, 2007, entitled “Method and System forAsymmetric PHY Operation For Ethernet A/V Bridging and Ethernet A/VBridging Extensions,” which is hereby incorporated herein by referencein its entirety.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to high speed wiredcommunication. More specifically, certain embodiments of the inventionrelate to a method and system for enabling video communication viaEthernet utilizing asymmetrical physical layer operations.

BACKGROUND OF THE INVENTION

The multimedia consumer electronics market is rapidly evolving withincreasingly sophisticated audio/video products. Consumers are becomingaccustomed to high definition video in their home entertainment centersas well as high end graphic capabilities on personal computers. Severalaudio/video interface standards have been developed to link a digitalaudio/video source, such as a set-top box, DVD player, audio/videoreceiver, digital camera, game console or personal computer with anaudio/video rendering device such as a digital television, a highdefinition video display panel or computer monitor. Examples of digitalvideo interface technology available for consumer electronics compriseHigh-Definition Multimedia Interface (HDMI), Display Port, Digital VideoInterface (DVI) and Unified Display Interface (UDI) for example. Theseaudio/video interfaces may each comprise unique physical interfaces andcommunication protocols.

As high data rates are required, new transmission technologies enablehigher transmission rates over copper cabling infrastructures. Variousefforts exist in this regard, including technologies that enabletransmission rates that may even reach 100 Gigabit-per-second (Gbps)data rates over existing cabling. For example, the IEEE 802.3 standarddefines the (Medium Access Control) MAC interface and physical layer(PHY) for Ethernet connections at 10 Mbps, 100 Mbps, 1 Gbps, and 10 Gbpsdata rates over twisted-pair copper cabling 100 m in length. With each10× rate increase more sophisticated signal processing is required tomaintain the 100 m standard cable range. Non-standard transmission ratescomprise 2.5 Gbps as well as 5 Gbps.

The specification for 10 Gigabit-per-second (Gbps) Ethernettransmissions over twisted-pair cabling (10GBASE-T) is intended toenable 10 Gbps connections over twisted-pair cabling at distances of upto 182 feet for existing cabling, and at distances of up to 330 feet fornew cabling, for example. To achieve full-duplex transmission at 10 Gbpsover four-pair twisted-pair copper cabling, elaborate digital signalprocessing techniques are needed to remove or reduce the effects ofsevere frequency-dependent signal attenuation, signal reflections,near-end and far-end crosstalk between the four pairs, and externalsignals coupled into the four pairs either from adjacent transmissionlinks or other external noise sources. New IEEE cabling specificationsare being considered for 40 Gbps and 100 Gbps rates.

There may be instances where the data rate required for transmission inone direction may be much higher than the data rate required fortransmission in the opposite direction, such as the delivery ofinteractive video from a central office to the consumer, for example. Inthis regard, the data rate for the transmission of video in onedirection may be much higher than the data rate required fortransmitting interactive commands in the opposite direction.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with the present invention as set forth inthe remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method for enabling video communication via Ethernetutilizing asymmetrical physical layer operations, substantially as shownin and/or described in connection with at least one of the figures, asset forth more completely in the claims.

Various advantages, aspects and novel features of the present invention,as well as details of an illustrated embodiment thereof, will be morefully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1A is a diagram illustrating an exemplary system for transfer ofvideo and/or audio data wherein a HDMI physical layer (PHY) is replacedwith an asymmetric multi-rate Ethernet physical layer (PHY) connection,in accordance with an embodiment of the invention.

FIG. 1B is a diagram illustrating an exemplary system for transfer ofgraphics or video data wherein a Display Port physical layer (PHY) isreplaced with an asymmetric multi-rate Ethernet physical layer (PHY)connection, in accordance with an embodiment of the invention.

FIG. 1C is a diagram illustrating an exemplary system for transfer ofvideo and/or audio data via a network wherein a HDMI physical layer(PHY) is replaced with an asymmetric multi-rate Ethernet physical layer(PHY) connection, in accordance with an embodiment of the invention.

FIG. 2A is a diagram illustrating an exemplary transfer of HDMIformatted video data over an Ethernet connection from an upstream linkpartner for example, a DVD player to a downstream link partner forexample, a HD video display panel, utilizing an asymmetric Ethernetmulti-rate PHY replacement of an HDMI PHY, in accordance with anembodiment of the invention.

FIG. 2B is a diagram illustrating an exemplary transfer of native videodata wherein video data may be encrypted and/or compressed prior totransmission over an Ethernet connection from an upstream link partner,for example, a DVD player to a downstream link partner, for example, aHD video display panel, utilizing an asymmetric Ethernet multi-rate PHY,in accordance with an embodiment of the invention.

FIG. 2C is a diagram illustrating an exemplary transfer of HDMIformatted video data over an Ethernet connection from an upstream linkpartner for example, a server to an Ethernet bridge and then to adownstream link partner for example, a client and video display panel,utilizing an asymmetric Ethernet multi-rate PHY replacement of an HDMIPHY, in accordance with an embodiment of the invention.

FIG. 3 is a block diagram illustrating an Ethernet system overtwisted-pair cabling link between an upstream link partner and adownstream link transmitting asymmetric data traffic, in connection withan embodiment of the invention.

FIG. 4 is a block diagram illustrating an exemplary Ethernet transceiverarchitecture comprising an asymmetric multi-rate PHY, in accordance withan embodiment of the invention.

FIG. 5 is a block diagram illustrating ECHO, NEXT, and FEXT channelconditions in an Ethernet system, in accordance with an embodiment ofthe invention.

FIG. 6 is a block diagram illustrating exemplary 10 Gigabit signalprocessing operations for received signals in an Ethernet systemutilized for asymmetric data traffic, in accordance with an embodimentof the invention.

FIG. 7 is a block diagram of a multi-rate Ethernet system for asymmetricdata traffic that utilizes 10 Gigabit signal processing resources in afour-pair extended range mode, in accordance with an embodiment of theinvention.

FIG. 8 is a block diagram of an exemplary echo canceller in an upstreamasymmetric multi-rate PHY with a 10 Gbps downstream data rate and a 1Mbps upstream data rate, in connection with an embodiment of theinvention.

FIG. 9 is a block diagram of a multi-rate Ethernet system for asymmetricdata traffic that utilizes 10 Gigabit signal processing resources in anasymmetric mode over fewer than 4 twisted pairs of wires, in accordancewith an embodiment of the invention.

FIG. 10 is a flow diagram illustrating exemplary steps in communicationrate reduction in Ethernet systems that utilize asymmetric multi-ratePHYs, in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and systemfor asymmetric physical layer (PHY) operations in video communicationsover Ethernet. Certain aspects of the invention may comprise reducingthe data rate of video transmission by an upstream asymmetric Ethernetmulti-rate PHY transceiver and transmitting via twisted-pair cabling toa downstream asymmetric Ethernet multi-rate PHY transceiver in aterminal device.

One embodiment of the invention may comprise a video processing systemcomprising asymmetric Ethernet multi-rate PHY and Ethernetfunctionality. In this regard, the asymmetric Ethernet multi-rate PHYand Ethernet functionality may replace HDMI video functionality utilizedin some systems. For example, in a downstream transceiver, theasymmetric Ethernet multi-rate PHY may receive HDMI encoded video, audioand/or auxiliary data and utilize asymmetric Ethernet multi-rate PHYtransceiver operations in place of HDMI PHY operations. In this regard,a source of HDMI encoded video audio and/or auxiliary data, for examplemay be a digital video disk (DVD) player that may be coupled with avideo display panel via an Ethernet interface connector and twisted-paircabling. The HDMI encoded video audio and/or auxiliary data may beprocessed by the asymmetric Ethernet multi-rate PHY transceiver in theDVD player and transported downstream via an Ethernet medium to anasymmetric Ethernet multi-rate PHY transceiver in the video displaypanel where the video and/or audio data may be rendered. The video datamay be in any format such as standard, enhanced or high definition videoformat and may be encrypted or un-encrypted and/or compressed oruncompressed. Notwithstanding, the video data may be processed byvarious video interface standards for example: HDMI, Display Port,Digital Visual Interface (DVI) or it may be native video for example.

Furthermore, the video, audio and/or auxiliary data may not be HDMIencoded. For example, native video data may be encapsulated via anEthernet media access control (MAC) processes within the DVD player. Inthis regard, the Ethernet encapsulated data may be processed by theasymmetric multi-rate Ethernet PHY transceiver and transporteddownstream via the Ethernet medium to the asymmetric multi-rate EthernetPHY transceiver and an Ethernet MAC process in the video display panelwhere the native video and/or audio may be rendered.

FIG. 1A is a diagram illustrating an exemplary system for transfer ofvideo and/or audio data utilizing an asymmetric multi-rate Ethernetphysical layer (PHY) connection, in accordance with an embodiment of theinvention. The asymmetric multi-rate Ethernet physical layer (PHY)connection may be utilized to replace, for example, a HDMI physicallayer (PHY). Referring to FIG. 1A, there is shown a DVD player 110, ahigh definition (HD) video display panel 112 and an Ethernet connection114.

The DVD player 110 may be a source of video and/or audio data that maybe accessible to users of the system. The DVD player 110 may becommunicatively coupled with the HD video display panel 112 and they maycommunicate via an Ethernet connection 114. In another embodiment of theinvention, the source of video and/or audio data may be for example aset-top box, a personal computer, a video game console and/or anaudio/video receiver.

The HD video display panel 112 may comprise suitable logic, circuitryand or code to render and display visual images and audio based onreceived video, audio and/or auxiliary data from the DVD player 110. TheHD video display panel 112 may be communicatively coupled with the DVDplayer 110 and they may communicate via an Ethernet connection 114.

The Ethernet connection 114 may comprise suitable logic, circuitryand/or code to support asymmetric multi-rate Ethernet PHY operations. Anexemplary Ethernet connection may comprise category 5, category 5 e,category 6, category 6 a, category 7 or better cabling for example.However, the invention is not limited in this regard, for example,category 3—type 2 cables may be utilized as well. Moreover, cables maybe shielded or unshielded. The Ethernet connection 114 may be enablequality of service mechanisms for example AN bridging. The Ethernetconnection 114 may be communicatively coupled with an Ethernet connectoron the video display panel 112 and an Ethernet connector on the DVDplayer 110. The DVD player 110 and the HD video display panel 112 may beenabled to exchange video, audio and/or auxiliary data via the Ethernetconnection 114. In this regard, the Ethernet connection 114 may be apoint to point connection between the DVD player 110 and the HD videodisplay panel 112. Moreover, the Ethernet connection 114 may span one ormore bridges within a network coupling the DVD player 110 and the HDvideo display panel 112. In this regard, Ethernet frames comprising thevideo, audio and/or auxiliary data may comprise a network address forthe DVD player 110 and/or the HD video display panel 112.

In operation, the DVD player 110 may comprise High Definition MultimediaInterface (HDMI) formatted video, audio and/or auxiliary data. The HDMIformatted video, audio and/or auxiliary data may contain informationthat may enable rendering of the video and/or audio data on the HD videodisplay panel 112. Physical layer operations typically performed by anHDMI interface may be replaced with the asymmetric Ethernet multi-ratePHY operations for transmission via the Ethernet connection 114 to theHD video display panel 112. The HDMI formatted video and/or audio maynot be encapsulated in Ethernet frames and/or may not utilize Ethernetaddressing for point to point communication as shown in FIG. 1A. Thevideo, audio and/or auxiliary data may be transmitted via the Ethernetconnection 114 utilizing the asymmetric Ethernet multi-rate PHY whereindown stream data may be transferred from the DVD player 110 to the HDvideo display panel 112 at a higher rate and upstream data transferredfrom the HD video display panel 112 to the DVD player 110 may betransferred at a lower rate. For example, video data may be transferreddownstream at a higher rate and control signals for example encryptionkeys and/or device identification may be transmitted upstream at a lowerrate.

FIG. 1B is a diagram illustrating an exemplary system for transfer ofgraphics or video data wherein a Display Port physical layer (PHY) isreplaced with an asymmetric multi-rate Ethernet physical layer (PHY)connection, in accordance with an embodiment of the invention. Referringto FIG. 1B, there is shown a work station or personal computer 118, avideo monitor 120 and an Ethernet connection 114.

The work station or personal computer 118 may comprise suitable logic,circuitry and or code to generate high end graphics or video data thatmay be transmitted to the video monitor 120 for rendering. The workstation or personal computer 118 may be communicatively coupled with thevideo monitor 120 and they may communicate via an Ethernet connection114.

The video monitor 120 may comprise suitable logic, circuitry and or codeto render and display graphic images and/or audio based on receivedvideo and/or audio data from the work station or personal computer 118.The video monitor 120 may be communicatively coupled with the workstation or personal computer 118 and they may communicate via anEthernet connection 114.

The Ethernet connection 114 may comprise suitable logic, circuitry andor code that may enable asymmetric multi-rate Ethernet PHY operations.An exemplary Ethernet connection may comprise category 5 category 5 e,category 6, category 6 a, category 7 or better cabling for example.However, the invention is not limited in this regard, for example,category 3—type 2 cables may be utilized as well. Moreover, cables maybe shielded or unshielded. The Ethernet connection 114 may be enablequality of service mechanisms for example AN bridging. The Ethernetconnection 114 may be communicatively coupled with an Ethernet connectoron the video monitor 120 and an Ethernet connector on the work stationor personal computer 118. The work station or personal computer 118 andthe video monitor 120 may be enabled to exchange video, audio and/orauxiliary data via the Ethernet connection 114. In this regard, theEthernet connection 114 may be a point to point connection between thework station or personal computer 118 and the video monitor 120.Moreover, the Ethernet connection 114 may span one or more bridgeswithin a network coupling the work station or personal computer 118 andthe video monitor 120. In this regard, Ethernet frames comprising thevideo, audio and/or auxiliary data may comprise a network address forthe work station or personal computer 118 and/or the video monitor 120.

In operation, the work station or personal computer 118 may generategraphics or video data. Rather than sending the graphics or video datato the video monitor 120 via a digital interface standard, for exampleDisplay Port (DP), the work station or personal computer 118 maygenerate DP packets from the graphics or video data and replace the DPPHY with the asymmetric Ethernet multi-rate PHY and send the DP packetsvia the Ethernet connection 114. The DP packets may also containinformation that may enable rendering of the graphics or video data onthe video monitor 120. Physical layer operations typically performed bya DP digital interface may be replaced with the asymmetric Ethernetmulti-rate PHY operations for transmission via the Ethernet connection114 to the video monitor 120. The graphics or video data may betransmitted via the Ethernet connection 114 utilizing the asymmetricEthernet multi-rate PHY wherein down stream data may be transferred fromthe a work station or personal computer 118 to the video monitor 120 ata higher rate and upstream data transferred from the video monitor 120to the work station or personal computer 118 may be transferred at alower rate. For example, graphics or video data may be transferreddownstream at a higher rate and/or lower bandwidth control signals, forexample encryption keys and/or device identification may be transmittedupstream at a lower rate.

FIG. 1C is a diagram illustrating an exemplary system for transfer ofvideo and/or audio data via a network utilizing an asymmetric multi-rateEthernet physical layer (PHY) connection, in accordance with anembodiment of the invention. Referring to FIG. 1C, there is shown avideo source device 130, a video destination device 132, an Ethernetconnection 114 and a network 134.

The video source device 130 may be accessible to users of the network.The video source device 130 may be communicatively coupled with thevideo destination device 132 via the Ethernet links 114 and the network134. In various embodiments of the invention, the source of video and/oraudio data may be for example a server, a personal computer, a videogame console and/or an audio/video receiver. The invention is notlimited to these examples and may comprise any suitable source of videodata.

The video destination device 132 may comprise suitable logic, circuitryand or code to render and display visual images and audio based onreceived video, audio and/or auxiliary data from the video source 130.The video destination device 132 may be for example a client connectedwith a video display or a television. The invention is not limited tothese examples and may comprise any suitable video destination devices.The video destination device 132 may be communicatively coupled with thevideo source device 130 via the Ethernet connections 114 and the network134.

The Ethernet connection 114 may comprise suitable logic, circuitryand/or code to support asymmetric multi-rate Ethernet PHY operations. Anexemplary Ethernet connection may comprise category 5, category 5 e,category 6, category 6 a, category 7 or better cabling for example.However, the invention is not limited in this regard, for example,category 3—type 2 cables may be utilized as well. Moreover, cables maybe shielded or unshielded. The Ethernet connection 114 may be enablequality of service mechanisms for example ANV bridging. The Ethernetconnection 114 may be communicatively coupled with an Ethernet connectoron the video source device 130 and an Ethernet connector on a devicewithin the network 134, for example an Ethernet bridge. In addition, theEthernet connection 114 may be communicatively coupled with the videodestination device 132. The video source device 130 and the videodestination device 132 may be enabled to exchange video, audio and/orauxiliary data via the Ethernet connection 114 and the network 134.

The network 134 may comprise suitable logic, circuitry and or code totransfer data between one or more data source devices and one or moredata destination devices. The network 134 may comprise one or moreEthernet bridges and may operate according to IEEE 802.1D standards forexample. The network 134 may be communicatively coupled with the videosource device 130 and the video destination device 132 via the Ethernetconnections 114.

In operation, the video source 130 may comprise High DefinitionMultimedia Interface (HDMI) formatted video, audio and/or auxiliarydata. The HDMI formatted video, audio and/or auxiliary data may containinformation that may enable rendering of the video and/or audio data onthe HD video display panel 112. Physical layer operations may beperformed by the asymmetric Ethernet multi-rate PHY operations fortransmission via the Ethernet connection 114 to the network 134. TheHDMI formatted video and/or audio may be encapsulated in Ethernet framesand may utilize Ethernet addressing for communication via network 134 asshown in FIG. 1C. The encapsulated video and/or audio may be sent to thenetwork 134 that may forward the data to one or more video destinationdevices 132. The video, audio and/or auxiliary data may be transmittedvia the Ethernet connection 114 utilizing the asymmetric Ethernetmulti-rate PHY. In addition, down stream data may be transferred fromthe video source device 130 to the video destination device 132 at ahigher rate than upstream data for example security and/or control datamay be received from the video destination device 132. Some embodimentsof the invention may enable A/V bridging for quality of serviceoperations. In this regard, adjustments may be made to the data withinone or more transmitted streams that may improve alignment in the timingof the multiple streams of data.

FIG. 2A is a diagram illustrating an exemplary transfer of HDMIformatted video data over an Ethernet connection from an upstream linkpartner for example, a DVD player to a downstream link partner forexample, a HD video display panel, utilizing an asymmetric Ethernetmulti-rate PHY replacement of an HDMI PHY, in accordance with anembodiment of the invention. Referring to FIG. 2A, there is shown a DVDplayer 110, an HD video display panel 112 and an Ethernet connection114. The DVD player 110 may comprise HDMI formatted video data 230 and aplurality of layered communication processes for example. The layeredcommunication processes may comprise HDMI encapsulation process 232,Ethernet medium access control (MAC) process 234 and Ethernet PHYprocess 236. The HD video display 112 may comprise HDMI formatted videodata 230 and a plurality of layered communication processes comprisingthe Ethernet PHY 238, the Ethernet MAC process 240 and the HDMIde-encapsulation process 242.

In one embodiment of the invention, the HDMI formatted video data 230may be accessed by an application that may be executing within the DVDplayer 110. The HDMI formatted video data 230 may be encapsulated by anHDMI process 232. The HDMI encapsulated video data may containinformation that enables rendering of the HDMI formatted video data 230on the HD video display panel 112. The HDMI encapsulation process 232may pass the HDMI encapsulated video data to the Ethernet MAC process234. The Ethernet MAC process 234 may enable scheduling of transmissionover the Ethernet connection 114 and may pass the HDMI encapsulatedvideo data and protocol and/or link management control signals to theEthernet PHY process 236. The Ethernet PHY process 236 may process theHDMI encapsulated video data with asymmetric multi-rate Ethernet PHYoperations and enable transport of the HDMI encapsulated video data tothe HD video display panel 112 via the Ethernet interface connection114. The HDMI encapsulated video data may be received by the HD videodisplay 112 via the asymmetric Ethernet PHY 238. The HDMI encapsulatedvideo data may be processed and passed up to the MAC layer 240. The MAClayer may process the data and pass it to the de-encapsulation layer 242wherein the HDMI formatted video is passed to higher layer processes andapplications for rendering via the HD video display 112.

In addition, lower rate data may travel in a reverse direction from theHD video display 112 to the DVD player 110. This lower rate data maycomprise control or security information for example. In this regard,the lower rate data may skip the HDMI blocks and undergo processing byEthernet MAC blocks 234 and 240 as well as Ethernet PHY blocks 236 and238.

FIG. 2B is a diagram illustrating an exemplary transfer of native videodata over an Ethernet connection from an upstream link partner, forexample, a DVD player to a downstream link partner, for example, a HDvideo display panel, utilizing an asymmetric Ethernet multi-rate PHY, inaccordance with an embodiment of the invention. Referring to FIG. 2B,there is shown a DVD player 110, an HD video display panel 112 and anEthernet connection 114. The DVD player 110 may comprise video data 250and a plurality of layered communication processes. The layeredcommunication processes may comprise an encryption/compression process252, a medium access control (MAC) process 234 and an Ethernet PHYprocess 236. The HD video display 112 may comprise video data 144 and aplurality of layered communication processes comprising an Ethernet PHY238, an Ethernet MAC process 240 and a de-encryption/decompressionprocess 254.

In various embodiments of the invention, the video data 250 may beaccessed by an application that may be executing within the DVD player110. The video data 250 may or may not be processed by theencryption/compression block 252. For example, video data may remainunencrypted and uncompressed and may be sent to the MAC process 234. Insome embodiments of the invention, the video data 250 may be encryptedbut not compressed for example or it may be compressed but not encryptedor it may be encrypted and compressed. Following theencryption/compression block 252, the video data may be passed to theEthernet MAC process 234.

The Ethernet MAC process 234 may enable scheduling of transmission overthe Ethernet connection 114 and may pass the encrypted and/or compressedvideo data and protocol and/or link management control signals to theEthernet PHY process 236. The Ethernet PHY process 236 may process withasymmetric multi-rate Ethernet PHY operations and enable transport ofthe encrypted and/or compressed video data to the HD video display panel112 via the Ethernet interface connection 114 for rendering and videodisplay.

In another embodiment of the invention, the Ethernet connection 114 mayspan one or more bridges between the upstream link partner and thedownstream link partner. In this regard, the Ethernet MAC process 234may encapsulate the video data in Ethernet frames. In addition, qualityof service mechanisms for example A/V bridging may be enabled.

The video data may be received by the HD video display 112 via theasymmetric Ethernet PHY 238. The video data may be processed and passedup to the MAC layer 240. The MAC layer 240 may process the data and passit to the de-encapsulation layer 242 wherein the video data is passed tohigher layer processes and one or more applications for rendering viathe HD video display 112.

In addition, lower rate data may travel in a reverse direction from theHD video display 112 to the DVD player 110. This lower rate data maycomprise control or security information for example. In this regard,the lower rate data may undergo processing by Ethernet MAC blocks 234and 240 as well as Ethernet PHY blocks 236 and 238.

FIG. 2C is a diagram illustrating an exemplary transfer of HDMIformatted video data via an Ethernet connection from a video source to avideo destination device utilizing an asymmetric Ethernet multi-ratePHY, in accordance with an embodiment of the invention. Referring toFIG. 2C, there is shown an exemplary video source for example, a server270, an Ethernet bridge 272, a client and video display 274 and anEthernet connection 114. The server 270 may comprise a plurality oflayered communication processes, and may handle storage and/orprocessing of HDMI formatted video data 230, for example. The layeredcommunication processes may comprise HDMI encapsulation process 232,Ethernet medium access control (MAC) process 234 and Ethernet PHYprocess 236. The Ethernet bridge 272 may comprise one or more layeredcommunication processes comprising Ethernet PHY 264, Ethernet MAC 262and Ethernet PHY 260. The client and video display 274 may comprise HDMIformatted video data 230 and a plurality of layered communicationprocesses that may comprise the Ethernet PHY 238, the Ethernet MACprocess 240 and the HDMI de-encapsulation process 242.

In one embodiment of the invention, the HDMI formatted video data 230may be accessed by an application that may be executing within theserver 270. The HDMI formatted video data 230 may be encapsulated by anHDMI process 232. The HDMI encapsulated video data may compriseinformation that enables rendering of the HDMI formatted video data 230on the client and video display 274. The HDMI encapsulation process 232in the server 270 may pass the HDMI encapsulated video data to theEthernet MAC process 234. The Ethernet MAC process 234 may enablescheduling of transmission over the Ethernet connection 114 and may passthe HDMI encapsulated video data, protocol and/or link managementcontrol signals to the Ethernet PHY process 236. The Ethernet PHYprocess 236 may process the HDMI encapsulated video data with asymmetricmulti-rate Ethernet PHY operations and enable transport of the HDMIencapsulated video data to the Ethernet Bridge 272 via the Ethernetconnection 114. The Ethernet bridge 272 may receive the HDMIencapsulated video data via the Ethernet PHY interface 260. The EthernetPHY 260 may process the received signals with symmetric Ethernet PHY orasymmetric multi-rate Ethernet PHY operations and pass the HDMIencapsulated video data to the Ethernet MAC 262. The Ethernet MACprocess 262 may enable scheduling of transmission via the Ethernetconnection 114 to the client and video display 274 and may pass the HDMIencapsulated video data, protocol and/or link management control signalsto the Ethernet PHY process 264. The Ethernet PHY process 264 mayprocess the HDMI encapsulated video data with symmetric Ethernet PHY orasymmetric multi-rate Ethernet PHY operations and enable transport ofthe HDMI encapsulated video data to the client and video display 274.The client and video display 274 may receive the HDMI encapsulated videovia the asymmetric Ethernet PHY 238. The asymmetric Ethernet PHY 238 maypass the HDMI encapsulated video data to Ethernet MAC 240 layer. TheEthernet MAC 240 layer may pass the HDMI encapsulated data to the HDMIde-encapsulation layer that may process the data and pass the data tohigher layer processes for rendering of the video data via anapplication on the client and video display 274.

In addition, lower rate data may travel in a reverse direction from theclient and video display 274 to one or more Ethernet bridges 272 and tothe server 270. This lower rate data may comprise control or securityinformation for example. In this regard, the lower rate data may skipthe HDMI blocks and undergo processing by Ethernet MAC blocks 234, 240and 262 as well as Ethernet PHY blocks 236, 238, 260 and 264.

FIG. 3 is a block diagram illustrating an Ethernet system overtwisted-pair cabling link between an upstream link partner and adownstream link partner for asymmetric data traffic, in connection withan embodiment of the invention. Referring to FIG. 3, there is shown asystem 300 that comprises an upstream link partner 302 and a downstreamlink partner 304. The upstream link partner 302 may comprise a hostprocessing block 306 a, a medium access control (MAC) controller 308 a,and a transceiver 304 a. The downstream link partner 304 may comprise adisplay video processing block 306 b, a MAC controller 308 b, and atransceiver 310 b. Notwithstanding, the invention is not limited in thisregard.

The upstream link partner 302 and the downstream link partner 304communicate via a cable 312. The cable 312 may be a four-pair unshieldedtwisted-pair (UTP) copper cabling, for example. Certain performanceand/or specifications criteria for UTP copper cabling have beenstandardized. An exemplary Ethernet connection may comprise category 5category 5 e, category 6, category 6 a, category 7 or better cabling forexample. However, the invention is not limited in this regard, forexample, category 3—type 2 cables may be utilized as well. Moreover,cables may be shielded or unshielded. For example, Category 5 orCategory 5 e cabling may provide the necessary performance for 10 MbpsEthernet transmissions over twisted-pair cabling (10BASE-T). In anotherexample, Category 5 cabling may provide the necessary performance for1000 Mbps, or Gbps, Ethernet transmissions over twisted-pair cabling(1000BASE-T). In some embodiments of the invention, non standard speedsfor example 2.5 Gbps and 5 Gbps may be utilized. In most instances, alower category cable may generally have a greater insertion loss than ahigher category cable.

The transceiver 310 a may comprise suitable logic, circuitry, and/orcode that may enable asymmetric Ethernet communication, such astransmission and reception of data, for example, between the upstreamlink partner 302 and the downstream link partner 304, for example. Inthis regard, the transceiver 310 a may enable transmission at a highdata rate to the downstream link partner 304 while also enablingreception at a low data rate from the downstream link partner 304.Similarly, the transceiver 310 b may comprise suitable logic, circuitry,and/or code that may enable asymmetric Ethernet communication betweenthe downstream link partner 304 and the upstream link partner 302, forexample. In this regard, the transceiver 310 b may enable transmissionat a low data rate to the upstream link partner 302 while also enablingreception at a high data rate from the upstream link partner 302.

The data transmitted and/or received by the transceivers 310 a and 310 bmay be formatted in a manner that may be compliant with the well-knownOSI protocol standard, for example. The OSI model partitions operabilityand functionality into seven distinct and hierarchical layers.Generally, each layer in the OSI model is structured so that it mayprovide a service to the immediately higher interfacing layer. Forexample, layer 1, or physical (PHY) layer, may provide services to layer2 and layer 2 may provide services to layer 3. In this regard, thetransceiver 310 a may enable PHY layer operations that are utilized forasymmetric data communication with the downstream link partner 304.Moreover, the transceiver 310 a may enable PHY layer operations that areutilized for asymmetric data communication with the upstream linkpartner 302.

The transceivers 310 a and 310 b may enable asymmetric multi-ratecommunications. In this regard, the data rate in the upstream and/or thedownstream direction may be <10 Mbps, 10 Mbps, 100 Mbps, 1000 Mbps (or 1Gbps) and/or 10 Gbps, for example. The transceivers 310 a and 310 b maysupport standard-based asymmetric data rates and/or non-standardasymmetric data rates. The transceivers 310 a and 310 b may utilizemultilevel signaling in their operation. In this regard, thetransceivers 310 a and 310 b may utilize pulse amplitude modulation(PAM) with various levels to represent the various symbols to betransmitted. For example, for 1000 Mbps Ethernet applications, a PAM5transmission scheme may be utilized in each twisted-pair wire, wherePAM5 refers to PAM with five levels {−2, −1, 0, 1, 2}. As a furtherexample, for 10 Gbps Ethernet applications, a PAM 16 scheme may beutilized in each twisted-pair wire with levels {−15, −13, −11, −9, −7,−5, −3, −1, 1, 3, 5, 7, 9, 11, 13, 15} where two successive PAM 16symbols are used to define a 128 point, two dimensional constellationreferred to in the IEEE 802.3 standard as 128 Double Square (DSQ).

The transceivers 310 a and 310 b may be configured to handle all thephysical layer requirements, which may include, but are not limited to,packetization, data transfer and serialization/deserialization (SERDES),in instances where such an operation is required. Data packets receivedby the transceivers 310 a and 310 b from MAC controllers 308 a and 308b, respectively, may include data and header information for each of theabove six functional layers. The transceivers 310 a and 310 b may beconfigured to encode data packets that are to be transmitted over thecable 312 and/or to decode data packets received from the cable 312.

The MAC controller 308 a may comprise suitable logic, circuitry, and/orcode that may enable handling of data link layer, layer 2, operabilityand/or functionality in the upstream link partner 302. Similarly, theMAC controller 308 b may comprise suitable logic, circuitry, and/or codethat may enable handling of layer 2 operability and/or functionality inthe downstream link partner 304. The MAC controllers 308 a and 308 b maybe configured to implement Ethernet protocols, such as those based onthe IEEE 802.3 standard, for example. Notwithstanding, the invention isnot limited in this regard.

The MAC controller 308 a may communicate with the transceiver 310 a viaan interface 314 a and with the host processing block 306 a via a buscontroller interface 316 a. The MAC controller 308 b may communicatewith the transceiver 310 b via an interface 314 b and with the displayvideo processing block 306 b via a bus controller interface 316 b. Theinterfaces 314 a and 314 b correspond to Ethernet interfaces thatcomprise protocol and/or link management control signals. The interfaces314 a and 314 b may be multi-rate interfaces. The bus controllerinterfaces 316 a and 316 b may correspond to PCI or PCI-X interfaces.Notwithstanding, the invention is not limited in this regard.

The host processing block 306 a and the display video processing block306 b may comprise suitable logic, circuitry and/or code to enablegraphics processing and/or rendering operations. The host processingblock 306 a and/or the display video processing block 306 b may comprisededicated graphics processors and/or dedicated graphics renderingdevices. The host processing block 306 a and the display videoprocessing block 306 b may be communicatively coupled with the MAC 308 aand the MAC 308 b respectively via the bus controller interfaces 316 aand 316 b respectively.

In the embodiment of the invention illustrated in FIG. 3, the hostprocessing block 306 a and the display video processing block 306 b mayrepresent layer 3 and above, the MAC controllers 308 a and 308 b mayrepresent layer 2 and above and the transceivers 310 a and 310 b mayrepresent the operability and/or functionality of layer 1 or the PHYlayer. In this regard, the host processing block 306 a and the displayvideo processing block 306 b may comprise suitable logic, circuitry,and/or code that may enable operability and/or functionality of the fivehighest functional layers for data packets that are to be transmittedover the cable 312. Since each layer in the OSI model provides a serviceto the immediately higher interfacing layer, the MAC controllers 308 aand 308 b may provide the necessary services to the host processingblock 306 a and the display video processing block 306 b to ensure thatdata are suitably formatted and communicated to the transceivers 310 aand 310 b. During transmission, each layer may add its own header to thedata passed on from the interfacing layer above it. However, duringreception, a compatible device having a similar OSI stack may strip offthe headers as the message passes from the lower layers up to the higherlayers.

FIG. 4 is a block diagram illustrating an exemplary Ethernet transceiverarchitecture comprising an asymmetric multi-rate PHY, in accordance withan embodiment of the invention. Referring to FIG. 4, there is shown alink partner 400 that may comprise a transceiver 402, a MAC controller404, a host processing block 406, an interface 408, and a bus controllerinterface 410.

The transceiver 402 may be an integrated device that comprises anasymmetric multi-rate PHY block 412, a plurality of transmitters 414 a,414 c, 414 e, and 414 g, a plurality of receivers 414 b, 414 d, 414 f,and 414 h, a memory 416, and a memory interface 418. The operation ofthe transceiver 402 may be the same as or substantially similar to thetransceivers 310 a and 310 b as described in FIG. 3. For example, whenthe transceiver 402 is utilized in an upstream link partner, thetransceiver 402 may enable a high rate for data transmission and a lowrate for data reception. In another example, when the transceiver 402 isutilized in a downstream link partner, the transceiver 402 may enable alow rate for data transmission and a high rate for data reception. Inthis regard, the transceiver 402 may provide layer 1 or PHY layeroperability and/or functionality that enables asymmetric data traffic.

Similarly, the operation of the MAC controller 404, the host processingblock 406, the interface 408, and the bus controller 410 may be the sameas or substantially similar to the respective MAC controllers 308 a and308 b, the host processing block 306 a and the display video processingblock 306 b, interfaces 314 a and 314 b, and bus controller interfaces316 a and 316 b as disclosed in FIG. 3. In this regard, the MACcontroller 404, the host processing block 406, the interface 408, andthe bus controller 410 may enable different data transmission and/ordata reception rates when implemented in an upstream link partner or adownstream link partner. The MAC controller 404 may comprise amulti-rate interface 404 a that may comprise suitable logic, circuitry,and/or code to enable communication with the transceiver 402 at aplurality of data rates via the interface 408.

The asymmetric multi-rate PHY block 412 in the transceiver 402 maycomprise suitable logic, circuitry, and/or code that may enableoperability and/or functionality of PHY layer requirements forasymmetric data traffic. The asymmetric multi-rate PHY block 412 maycommunicate with the MAC controller 404 via the interface 408. In oneaspect of the invention, the interface 408 may be configured to utilizea plurality of serial data lanes for receiving data from the asymmetricmulti-rate PHY block 412 and/or for transmitting data to the asymmetricmulti-rate PHY block 412, in order to achieve higher operational speedssuch as Gbps, 10 Gbps or higher speeds for example. The asymmetricmulti-rate PHY block 412 may be configured to operate in one or more ofa plurality of communication modes, where each communication modeimplements a different communication protocol. These communication modesmay include, but are not limited to, IEEE 802.3, 10GBASE-T, othersimilar protocols and/or non-standard communication protocols thatenable asymmetric data traffic. The asymmetric multi-rate PHY block 412may be configured to operate in a particular mode of operation uponinitialization or during operation. The asymmetric multi-rate PHY block412 may also be configured to operate in an extended range mode.

The asymmetric multi-rate PHY block 412 may be coupled to memory 416through the memory interface 418, which may be implemented as a serialinterface or a bus. The memory 416 may comprise suitable logic,circuitry, and/or code that may enable storage or programming ofinformation that includes parameters and/or code that may effectuate theoperation of the asymmetric multi-rate PHY block 412. The parameters maycomprise configuration data and the code may comprise operational codesuch as software and/or firmware, but the information need not limitedin this regard. Moreover, the parameters may include adaptive filterand/or block coefficients for use by the asymmetric multi-rate PHY block412, for example.

The transmitters 414 a, 414 c, 414 e, and 414 g may comprise suitablelogic, circuitry, and/or code that may enable transmission of data froma transmitting link partner to a remote link partner via the cable 312in FIG. 3, for example. In this regard, when the transmitting linkpartner is an upstream link partner, the transmitters 414 a, 414 c, 414e, and 414 g may operate at a higher data rate than the data ratereceived from the downstream link partner. Similarly, when the when thetransmitting link partner is a downstream link partner, the transmitters414 a, 414 c, 414 e, and 414 g may operate at a lower data rate than thedata rate received from the upstream link partner.

The receivers 414 b, 414 d, 414 f, and 414 h may comprise suitablelogic, circuitry, and/or code that may enable receiving data from aremote link partner via the cable 312, for example. In this regard, whenthe receiving link partner is an upstream link partner, the receivers414 b, 414 d, 414 f, and 414 h may operate at a lower data rate than thedata rate transmitted to the downstream link partner. Similarly, whenthe when the receiving link partner is a downstream link partner, thereceivers 414 b, 414 d, 414 f, and 414 h may operate at a higher datarate than the data rate transmitted to the upstream link partner.

Each of the four pairs of transmitters and receivers in the transceiver402 may correspond to one of the four wire pairs in the cable 312. Forexample, transmitter 414 a and receiver 414 b may be utilized toasymmetrically communicate data with a remote link partner via the firstwire pair in the cable 312. Similarly, transmitter 414 g and receiver414 h may be utilized to asymmetrically communicate data with a remotelink partner via the fourth wire pair in the cable 312. In this regard,at least one of the four transmitter/receiver pairs may be enabled toprovide the appropriate communication rate. The above-disclosed schememay be applied to fewer, or greater, number of wires, for example.

FIG. 5 is a block diagram illustrating ECHO, NEXT, and FEXT channelconditions in an Ethernet system, in accordance with an embodiment ofthe invention. Referring to FIG. 5, there is shown an asymmetricEthernet system 500 that may comprise an upstream link partner 501 a anda downstream link partner 501 b. The upstream link partner 501 a and thedownstream link partner 501 b may asymmetrically communicate data viafour twisted-pair wires 510 in full duplex operation. Each of the fourtwisted-pair wires 510 may support a portion of the data rates that maybe necessary to provide the aggregate upstream and downstream datatraffic. In this regard, each of the four twisted-pair wires 510 maysupport an equal or even or an unequal or uneven portion of theaggregate upstream and downstream data traffic.

The upstream link partner 501 a may comprise four hybrids 506. Eachhybrid 506 in the upstream link partner 501 a may be communicativelycoupled to a transmitter 502 a, a receiver 504 a, and to one of the fourtwisted-pair wires 510. Similarly, the downstream link partner 501 b maycomprise four hybrids 506. Each hybrid 506 in the downstream linkpartner 501 b may be communicatively coupled to a transmitter 502 b, areceiver 504 b, and to one of the four twisted-pair wires 510. Theportions of the upstream link partner 501 a and the downstream linkpartner 501 b shown in FIG. 5 may correspond to a portion of thephysical (PHY) layer operations supported by the upstream link partner501 a and by the downstream link partner 501 b respectively.

Each hybrid 506 in the upstream link partner 501 a or in the downstreamlink partner 501 b may be communicatively coupled to or comprise atransformer 508. The hybrid 506 may comprise suitable logic, circuitry,and/or code that may enable separating the transmitted and receivedsignals from a twisted-pair wire 510. The transmitters 502 a and 502 bmay comprise suitable logic, circuitry, and/or code that may enablegenerating signals to be transmitted to a link partner at the other endof the link via a hybrid 506 and a twisted-pair wire 510. In thisregard, the transmitters 502 a may operate at a higher data rate thanthe transmitters 502 b. The receivers 304 may comprise suitable logic,circuitry, and/or code that may enable processing signals received froma link partner at the other end of the link via a twisted-pair wire 510and a hybrid 506. In this regard, the receivers 504 a may operate at alower data rate than the receivers 504 b.

During operation, several conditions may occur in each of thetwisted-pair wires 510. For example, intersymbol interference (ISI) mayoccur as a result of frequency dependent wire attenuation. As shown inFIG. 5, an ECHO component may be received in a twisted-pair wire 510from an echo that results from the transmitter 502 a in the upstreamlink partner 501 a on the same twisted-pair wire 510. A near-endcrosstalk (NEXT) component may also be received in a twisted-pair wire510 from the local transmitters 502 a corresponding to the threeadjacent twisted-pair wires 510 in the upstream link partner 501 a.Moreover, a far-end crosstalk (FEXT) component may also be received in atwisted-pair wire 510 from the transmitters 502 b in the downstream linkpartner 501 b at the other end of the link. Similar conditions may alsooccur in the downstream link partner 501 b, for example.

FIG. 6 is a block diagram illustrating exemplary 10 Gigabit signalprocessing operations for receive and transmit signals in an Ethernetsystem utilized for asymmetric data traffic, in accordance with anembodiment of the invention. Referring to FIG. 6, there is shown asignal processing system 600 that may provide a portion of the signalprocessing performed by the physical (PHY) layer operations in anEthernet transceiver that supports asymmetric multi-rate operation. Forexample, the signal processing system 600 may be implemented in theasymmetric multi-rate PHY block 412 and/or in the receivers 414 b, 414d, 414 f, and 414 h in FIG. 4. The signal processing system 600 maycomprise an analog-to-digital converter (A/D) 602, a matrix feed-forwardequalizer (FFE) 604, NEXT cancellers 606, an adder 608, an ECHOcanceller 610, a low density parity check code (LDPC) decoder 612, anadaptive pre-filter 614, an LDPC encoder 620, a 128 Double Square (DSQ)mapper 622 a Tomlinson Harashima pre-coder (THP) 624 and a digital toanalog converter 626.

The A/D 602 may comprise suitable logic, circuitry, and/or code that mayenable converting analog signals received via a twisted-pair wire intodigital signals. The output of the A/D 602 may be communicated to thematrix FFE 604. The matrix FFE 604 may comprise suitable logic,circuitry, and/or code that may enable removal of precursor ISI to makethe channel minimum-phase and to whiten the noise in the channel. TheNEXT cancellers 606 may comprise suitable logic, circuitry, and/or codethat may enable canceling at least a portion of the NEXT componentreceived in the twisted-pair wire from the local transmitterscorresponding to the three adjacent twisted-pair wires. The ECHOcanceller 610 may comprise suitable logic, circuitry, and/or code thatmay enable canceling at least a portion of the ECHO component receivedin the twisted-pair wire from the local transmitter on the sametwisted-pair wire.

The adder 608 may comprise suitable logic, circuitry, and/or code thatmay enable adding the output of the matrix FFE 604, the NEXT cancellers606, and/or the ECHO canceller 610 to generate a postcursor channelimpulse response, Z_(n,1). The adaptive pre-filter 614 and the LDPCdecoder 612 may comprise suitable logic, circuitry and/or code that mayenable mitigating the ISI that may result from the postcursor impulseresponse and, decoding low density parity check coded data. The adaptivepre-filter 614 and LDPC decoder 612 may receive as inputs the postcursorchannel impulse responses, z_(n,2), z_(n,3), and z_(n,4) correspondingto the other twisted-pair wires. The LDPC decoder 612 may generate thedetected bits that correspond to the received analog signal.

Prior to an Ethernet transmission, the low density parity check code(LDPC) encoder 620 may comprise suitable logic, circuitry and/or codefor enabling error correction. The output of the LDPC encoder 620 may besent to the 128 DSQ mapper 622. The 128 DSQ mapper 622 may be utilizedin the implementation of 16 level pulse amplitude modulation 16 (PAM16)for each twisted-pair wire. The output of the 128 DSQ mapper 622 may besent to the THP 624. The THP 624 may comprise four THPs, one for eachtwisted pair. The THP 624 may comprise suitable logic, circuitry and orcode that may enable spectral shaping in the transmitter and thus reducereceiver complexity. The output of the THP 624 may be communicated tothe DAC 626. The DAC 626 may comprise suitable logic, circuitry and/orcode that may enable converting signals from digital to analog fortransmission via a twisted-pair wire cabling. The invention is notlimited with regard to any specific signal processing operations orfunctionality. Any suitable signal processing methods and/or system maybe utilized.

FIG. 7 is a block diagram of a multi-rate Ethernet system for asymmetricdata traffic that utilizes 10 Gigabit signal processing resources in afour-pair extended range mode, in accordance with an embodiment of theinvention. Referring to FIG. 7, there is shown an asymmetric multi-rateEthernet system 700 that may comprise an upstream link partner 701 a anda downstream link partner 701 b. The upstream link partner 701 a maycorrespond to, for example, the entry DVD player in FIG. 1, while thedownstream link partner 701 b may correspond to, for example, the highdefinition video display panel 112. The asymmetric multi-rate Ethernetsystem 700 may support a plurality of asymmetric data rates or modes ofoperation over four-pair twisted-pair wire, including the ability toprovide 1 Gbps or 10 Gbps, for example as shown in FIG. 7. In anotherembodiment of the invention, the asymmetric multi-rate Ethernet system700 may operate in an extended range mode of operation that provides 10Mbps in the downstream direction and 2 Mbps in the upstream direction,for example. In this regard, the extended range operation may beachieved by utilizing the 2 Mbps and 10 Mbps lower communication datarates, that is, data rates below the 1 Gbps or 10 Gbps that may beachieved by the signal processing operations enabled in either theupstream link partner 701 a or the downstream link partner 701 b.

The upstream link partner 701 a may comprise four hybrids 506 asdescribed in FIG. 5. Notwithstanding, the invention is not so limitedand may support various implementations of a hybrid circuitry. Eachhybrid 506 in the upstream link partner 701 a may be communicativelycoupled to a transmitter 502 a, a receiver 504 a, and to one of the fourtwisted-pair wires 510 also as described in FIG. 5. Associated with eachhybrid 506 in the upstream link partner 701 a may also be an echocanceller 702 a and a subtractor 704 a. The upstream link partner 701 amay also comprise a demultiplexer (demux) 706 a, an aligner 708 a, and amultiplexer (mux) 710 a.

Similarly, the downstream link partner 701 b may comprise four hybrids506. Each hybrid 506 in the downstream link partner 701 b may becommunicatively coupled to a transmitter 502 b, a receiver 504 b, and toone of the four twisted-pair wires 510 as described in FIG. 5.Associated with each hybrid 506 in the downstream link partner 701 b arealso an echo canceller 504 b and a subtractor 506 b. The remote linkpartner 701 b may also comprise a demux 706 b, an aligner 708 b, and amux 710 b. The portions of the upstream link partner 701 a anddownstream link partner 701 b shown in FIG. 7 may correspond to aportion of the physical (PHY) layer operations supported by the upstreamlink partner 701 a and downstream link partner 701 b respectively.

The demux 706 a may comprise suitable logic, circuitry, and/or code thatmay enable separating an exemplary 10 Gbps downstream signal into four2.5 Gbps signals for transmission over the four twisted-pair wires.Similarly, the demux 706 b may comprise suitable logic, circuitry,and/or code that may enable separating an exemplary 1 Gbps upstreamsignal into four 250 Mbps signals for transmission over the fourtwisted-pair wires. The aligner 708 a may comprise suitable logic,circuitry, and/or code that may enable aligning the 250 Mbps signalsreceived from each of the four twisted-pair wires by the upstream linkpartner 701 a. Similarly, the aligner 708 b may comprise suitable logic,circuitry, and/or code that may enable aligning the 2.5 Gbps signalsreceived from each of the four twisted-pair wires by the downstream linkpartner 701 b. The mux 710 a may comprise suitable logic, circuitry,and/or code that may enable combining the aligned 250 Mbps signals fromthe aligner 708 a to generate the received 1 Gbps upstream signal.Similarly, the mux 710 b may comprise suitable logic, circuitry, and/orcode that may enable combining the aligned 2.5 Gbps signals from thealigner 708 a to generate the received 10 Gbps downstream signal.

The echo cancellers 702 a and 702 b may comprise suitable logic,circuitry, and/or code that may enable at least partial cancellation ofthe ECHO component in the corresponding signal received via thereceivers 504 a and 504 b, respectively, associated with the sametwisted-pair wire. The subtractors 704 a and 704 b may comprise suitablelogic, circuitry, and/or code that may enable cancellation of the ECHOcomponent from the received signal.

In operation, the upstream link partner 701 a may separate a 10 Gbpssignal to be transmitted into four 2.5 Gbps signals via the demux 706 a.Each signal to be transmitted is processed by a transmitter 502 a beforebeing communicated to the corresponding twisted-pair wire via a hybrid506. The four transmitted signals may arrive at the downstream linkpartner 701 b, where each of the signals may be processed by a receiver504 b before echo cancellation occurs from the operation of acorresponding echo canceller 702 b and subtractor 704 b. The fourreceived 2.5 Gbps signals may be aligned in the aligner 708 b beforebeing combined in the mux 710 b into a 10 Gbps received downstreamsignal.

Similarly, the downstream link partner 701 b may separate a 1 Gbpssignal to be transmitted into four 250 Mbps signals via the demux 706 b.Each signal to be transmitted may be processed by a transmitter 502 bbefore being communicated to the corresponding twisted-pair wire via ahybrid 506. The four transmitted signals may arrive at the upstream linkpartner 701 a, where each of the signals may be processed by a receiver504 a before echo cancellation occurs from the operation of acorresponding echo canceller 702 a and subtractor 704 a. The fourreceived 500 kbps signals may be aligned in the aligner 708 a beforebeing combined in the mux 710 a into a 1 Gbps received upstream signal.

The upstream link partner 701 a and the downstream link partner 701 bmay communicate via all four twisted-pair wires 510 in full duplexoperation to provide an aggregate of 1 Gbps for the upstream data rateand 10 Gbps for the downstream data rate. Reducing the communicationrate to 2 Mbps and 10 Mbps from, for example, 100 Mbps or higher, whileutilizing the higher communication rate PHY layer signal processingoperations, may enable extending the range, that is, extending thestandard length, of the twisted-pair wires 510. In this regard, theasymmetric multi-rate operations of the upstream link partner 701 a anda downstream link partner 701 b may support Gigabit PHY layer operationsthat may utilize multi-level signaling to transmit multiple bits perclock interval. PAM-5 may be used to transmit 2 bits per symbol andreduce the symbol rate to carry on each twisted-pair wire 510. In thisregard, multi-level signaling may be applied at 100 Mbps, 10 Mbps, or<10 Mbps rates, that is, at lower communication rates, to permitoperation at reduced symbol rates. For example, 25 Mbps may be carriedon a single twisted-pair wire at a 12.5 Msps symbol rate. Reducing thesymbol rate enables transmission over longer cable ranges. The signalprocessing operations available in a Gigabit PHY layer may support 2, 3,4, or 5 levels of signaling with no increase in complexity, for example.

Reducing the communication rate may also enable utilizing cabling withhigher insertion loss while maintaining the same standard length. Forexample, for Gigabit operations, a Category 5 or Category 5 e cable maybe utilized. Reducing the communication rate in one direction in theasymmetric data traffic to 100 Mbps, for example, may enable utilizingcabling with higher insertion loss than a Category 5 or Category 5 ecabling while maintaining the 100 m length requirement under the IEEE802.3 standard. The insertion loss of a twisted-pair wire cableincreases as the square root of frequency. Insertion loss, in dB, isdirectly proportional to cable length. Applying Gigabit signalprocessing operation at 100 Mbps data rate may increase the cable range.NEXT cancellation operations also improve the SNR of each receivedsignal and may be applied at 100 Mbps and 10 Mbps rates to achievesimilar improvements in SNR and further extend the cable range at thosereduced communication rates.

The asymmetric multi-rate Ethernet system 700 need not be limited toachieving a lower communication rate in any one direction by evenlydistributing the data rate over each of the four twisted-pair wiresutilized. In another embodiment of the invention, the asymmetricmulti-rate Ethernet system 700 may achieve a lower communication rate bydistributing the data rate unevenly over each of the four twisted-pairwires utilized. For example, for a 10 Mbps downstream data rate, thefirst twisted-pair wire may support 1 Mbps, the second twisted-pair wiremay support 2 Mbps, the third twisted-pair wire may support 3 Mbps, andthe fourth twisted-pair wire may support 4 Mbps, to achieve an aggregateof 10 Mbps. A similar approach may be followed for generating anaggregate upstream data rate from unevenly distributed data rates overeach of the four twisted-pair wires utilized. In this regard, thecomponents in the upstream link partner 701 a and/or the downstream linkpartner 701 b may be adapted to handle an unevenly distributed lowercommunication rate.

FIG. 8 is a block diagram of an exemplary echo canceller in an upstreamasymmetric multi-rate PHY with a higher downstream data rate and a lowerupstream data rate, in connection with an embodiment of the invention.Referring to FIG. 8, there is shown an echo canceller 806 in a portionof an asymmetric multi-rate transceiver in an upstream link partner thatis utilized in a mode of operation that supports 10 Gbps downstream datarate and 1 Mbps upstream data rate. The echo canceller 806 may beimplemented utilizing an N tap echo canceller architecture that utilizesN/10 multipliers, for example. In this regard, the echo canceller 806may utilize a plurality of registers 810, a plurality of multipliers814, a plurality of delay taps 812, a plurality of adders 816, an outputregister 818, and a switch 820.

The echo canceller 806 may utilize a digital downstream signal that isbased on a transmission clock, F_(TX), to generate an output signal viathe switch 820 to be communicated to an adder 808, where the outputsignal is based on a receive clock, F_(RX)=F_(TX)/10. The digitaldownstream signal may be converted to an analog downstream signal by thedigital-to-analog converter (DAC) 802 for transmission via atwisted-pair copper wire 822. An analog upstream signal may be receivedby an analog-to-digital converter (ADC) 804 for conversion to a digitalupstream signal in the upstream link partner. The digital upstreamsignal and the output signal generated by the echo canceller 806 may beadded in the adder 808 to reduce the ECHO component in the receiveddigital upstream signal.

FIG. 9 is a block diagram of a multi-rate Ethernet system for asymmetricdata traffic that utilizes Gigabit signal processing resources in atwo-pair extended range mode, in accordance with an embodiment of theinvention. Referring to FIG. 9, there is shown an asymmetric multi-rateEthernet system 900 that may comprise an upstream link partner 901 a anda downstream link partner 901 b. The asymmetric multi-rate Ethernetsystem 900 may support a communication rate, for example, 10 Gbpsdownstream and 1 Gbps upstream. The asymmetric multi-rate Ethernetsystem 900 may also support other modes of operation, such as a lowerasymmetric transmission rate over two-pair twisted-pair wire. In thisregard, the asymmetric multi-rate Ethernet system 900 may support alower communication rate, such as 10 Mbps downstream data rate and 2Mbps upstream data rate, while utilizing the signal processingoperations available in the asymmetric multi-rate PHY layer forprocessing the higher communication rate, such as 1 Gbps or 10 Gbps whenavailable.

The upstream link partner 901 a and the downstream link partner 901 bmay communicate, for example, via two Category 5 twisted-pair wires 510in full duplex operation. A 5 Gbps downstream data rate at each wire mayprovide an aggregate downstream data rate of 10 Gbps and a 500 Mbpsupstream data rate at each wire may provide an aggregate upstream datarate of 1 Gbps. The upstream link partner 901 a may utilize two hybrids506 with corresponding echo canceller 902 a and a subtractor 904 a. Theupstream link partner 901 a may also utilize a demux 906 a, an aligner908 a, and a mux 910 a for transmission and reception of signals at thereduced asymmetric communication rate. Similarly, the downstream linkpartner 901 b may utilize two hybrids 506 with corresponding echocanceller 902 b and a subtractor 904 b. The downstream link partner 901b may also utilize a demux 906 b, an aligner 908 b, and a mux 910 b fortransmission and reception of signals at the reduced asymmetriccommunication rate. The two remaining twisted-pair wires may remainunused in the asymmetric multi-rate Ethernet system 900.

The asymmetric multi-rate Ethernet system 900 need not be limited toachieving a lower asymmetric communication rate by evenly distributingthe data rate over each of the two twisted-pair wires utilized. Inanother embodiment of the invention, the asymmetric multi-rate Ethernetsystem 800 may achieve a lower communication rate by distributing theupstream and downstream data rates unevenly over each of the twotwisted-pair wires utilized. For example, the first twisted-pair wiremay support a 4 Gbps downstream data rate while the second twisted-pairwire may support 6 Gbps downstream data rate, to achieve an aggregate of10 Gbps. Similarly, the first twisted-pair wire may support a 800 Mbpsupstream data rate while the second twisted-pair wire may support 200Mbps upstream data rate, to achieve an aggregate of 1 Gbps In thisregard, the components in the upstream link partner 901 a and/or thedownstream link partner 901 b may be adapted to handle an unevenlydistributed lower communication rate with asymmetric data traffic.

FIG. 10 is a flow diagram illustrating exemplary steps in communicationrate reduction to achieve extended range in Ethernet systems thatutilize asymmetric multi-rate PHYs, in accordance with an embodiment ofthe invention. Referring to FIG. 10, there is shown a flow diagram 1000.After start step 1002, in step 1004, an asymmetric Gigabit Ethernettransceiver may be enabled. The Gigabit Ethernet transceiver may utilizean asymmetric multi-rate PHY layer that enables reducing thecommunication rate from, for example, 1 Gbps to a lower communicationrate. The lower communication rate may be a 10 Mbps downstream data rateand a 2 Mbps upstream data rate, for example, but need not be solimited. The asymmetric multi-rate PHY layer may also enable reductionof the symbol rate for the asymmetric Gigabit Ethernet transceiver. Whenreducing the communication rate or symbol rate, the asymmetricmulti-rate PHY layer enables the application of Gigabit signalprocessing operations to the reduced communication or symbol rate.

In step 1006, an extended range mode may be enabled in the asymmetricGigabit Ethernet transceiver whereby the asymmetric multi-rate PHY layerreduces the communication rate and/or the symbol rate in at least one ofthe communication directions. In step 1008, at least a portion of theasymmetric Gigabit signal processing operations available in theasymmetric multi-rate PHY layer may be utilized during the extendedrange mode to enable the use of longer cables or to enable the use ofhigher insertion loss cables at the standard length. After step 1008,the process may proceed to end step 1010.

In an embodiment of the invention, signals may be communicated between avideo signal source 110 and a video rendering device 112 via anasymmetrical multi-rate Ethernet physical layer (PHY). In this regard,the symbol rate may be reduced from a higher communication rate to alower communication rate. The asymmetric multi-rate Ethernet PHY 412 maybe enabled to support multiple rates. The asymmetrical multirateEthernet PHY may be enabled to handle compressed and/or uncompressed,encrypted and/or unencrypted video signals as shown in FIG. 2B block 132and FIG. 2C wherein, encryption and/or compression blocks are not shown.A communication rate of the signals communicated between the videosignal source 110 and the video rendering device 112 may be reduced froma higher symbol rate to a lower symbol rate. One or more of thecommunicated signals may be modified by an echo cancellation operation,a near end cross talk (NEXT) cancellation operation, forward errorcorrection (FEC) and/or a far end cross talk (FEXT) cancellationoperation. The video signals communicated from the video signal source110 to the video rendering device 112 may be equalized. An aggregatecommunication rate may be evenly or unevenly distributed among one ormore links 114 coupling the video signal source to the video renderingdevice. A plurality of links 114 coupling the video signal source 110 tosaid video rendering device 112 may also be aggregrated.

Another embodiment of the invention may provide a machine-readablestorage, having stored thereon, a computer program having at least onecode section executable by a machine, thereby causing the machine toperform the steps as described herein for enabling video communicationvia asymmetrical Ethernet physical layer devices.

Accordingly, the present invention may be realized in hardware,software, or a combination of hardware and software. The presentinvention may be realized in a centralized fashion in at least onecomputer system or in a distributed fashion where different elements arespread across several interconnected computer systems. Any kind ofcomputer system or other apparatus adapted for carrying out the methodsdescribed herein is suited. A typical combination of hardware andsoftware may be a general-purpose computer system with a computerprogram that, when being loaded and executed, controls the computersystem such that it carries out the methods described herein.

The present invention may also be embedded in a computer programproduct, which comprises all the features enabling the implementation ofthe methods described herein, and which when loaded in a computer systemis able to carry out these methods. Computer program in the presentcontext means any expression, in any language, code or notation, of aset of instructions intended to cause a system having an informationprocessing capability to perform a particular function either directlyor after either or both of the following: a) conversion to anotherlanguage, code or notation; b) reproduction in a different materialform.

While the present invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiment disclosed, but that the present invention willinclude all embodiments falling within the scope of the appended claims.

1. A method for wired communication, the method comprising:communicating signals between a video signal source and a videorendering device coupled to said video signal source, wherein each ofsaid video signal source and said video rendering device comprises anasymmetric multi-rate Ethernet physical layer (PHY) that handles saidcommunication of said signals.
 2. The method according to claim 1,wherein said asymmetric multi-rate Ethernet PHY handles compressedand/or uncompressed video signals.
 3. The method according to claim 1,wherein said asymmetric multi-rate Ethernet PHY handles encrypted and/orunencrypted video signals.
 4. The method according to claim 1, whereinsaid asymmetric multi-rate Ethernet PHY handles data with quality ofservice requirements.
 5. The method according to claim 4, wherein saidquality of service is provided by AV bridging.
 6. The method accordingto claim 1, comprising reducing a communication rate of said signalscommunicated between said video signal source and said video renderingdevice from a higher symbol rate to a lower symbol rate.
 7. The methodaccording to claim 1, comprising modifying one or more of saidcommunicated signals via at least one of an echo cancellation operation,a near end cross talk (NEXT) cancellation operation, a far end crosstalk (FEXT) cancellation operation and a forward error correction (FEC)operation.
 8. The method according to claim 1, comprising equalizingvideo signals communicated from said video signal source to said videorendering device.
 9. The method according to claim 1, comprisingdistributing an aggregate communication rate evenly or unevenly amongone or more links coupling said video signal source to said videorendering device.
 10. The method according to claim 9, comprising timealigning said communication of said signals among one or more linkscoupling said video signal source to said video rendering device. 11.The method according to claim 9, comprising aggregating a plurality oflinks coupling said video signal source to said video rendering device.12. The method according to claim 1, comprising communicating saidsignals between said video signal source and a plurality of videorendering devices comprising said asymmetric multi-rate Ethernet PHY.13. A system for wired communication, the system comprising: one or morecircuits that enable communicating signals between a video signal sourceand a video rendering device coupled to said video signal source,wherein each of said video signal source and said video rendering devicecomprises an asymmetric multi-rate Ethernet physical layer (PHY) thathandles said communication of said signals.
 14. The system according toclaim 13, wherein said asymmetric multi-rate Ethernet PHY handlescompressed and/or uncompressed video signals.
 15. The system accordingto claim 13, wherein said asymmetric multi-rate Ethernet PHY handlesencrypted and/or unencrypted video signals.
 16. The system according toclaim 13, wherein said asymmetric multi-rate Ethernet PHY handles datawith quality of service requirements.
 17. The system according to claim16, wherein said quality of service is provided by audio visual (AV)bridging.
 18. The system according to claim 13, wherein said one or morecircuits reduces a communication rate of said signals communicatedbetween said video signal source and said video rendering device from ahigher symbol rate to a lower symbol rate.
 19. The system according toclaim 13, wherein said one or more circuits modifies one or more of saidcommunicated signals via at least one of an ECHO cancellation operation,a NEXT cancellation operation, a FEXT cancellation operation and a FECoperation.
 20. The system according to claim 13, wherein said one ormore circuits enables equalization of video signals communicated fromsaid video signal source to said video rendering device.
 21. The systemaccording to claim 13, wherein said one or more circuits enablesdistribution of an aggregate communication rate evenly or unevenly amongone or more links coupling said video signal source to said videorendering device.
 22. The method according to claim 21, comprising timealigning said communication of said signals among one or more linkscoupling said video signal source to said video rendering device. 23.The system according to claim 21, wherein said one or more circuitsenables aggregation of a plurality of links coupling said video signalsource to said video rendering device.
 24. The method according to claim13, comprising communicating said signals between said video signalsource and a plurality of video rendering devices comprising saidasymmetric multi-rate Ethernet PHY.
 25. A machine-readable storagehaving stored thereon, a computer program having at least one codesection for wired communication, the at least one code section beingexecutable by a machine for causing the machine to perform stepscomprising: communicating signals between a video signal source and avideo rendering device coupled to said video signal source, wherein eachof said video signal source and said video rendering device comprises anasymmetric multi-rate Ethernet physical layer (PHY) that handles saidcommunication of said signals.
 26. The machine-readable storageaccording to claim 25, wherein said asymmetric multi-rate Ethernet PHYhandles compressed and/or uncompressed video signals.
 27. Themachine-readable storage according to claim 25, wherein said asymmetricmulti-rate Ethernet PHY handles encrypted and/or unencrypted videosignals.
 28. The machine-readable storage according to claim 25, whereinsaid asymmetric multi-rate Ethernet PHY handles data with quality ofservice requirements.
 29. The machine-readable storage according toclaim 28, wherein said quality of service is provided by AV bridging.30. The machine-readable storage according to claim 25, wherein said atleast one code section comprises code for reducing a communication rateof said signals communicated between said video signal source and saidvideo rendering device from a higher symbol rate to a lower symbol rate.31. The machine-readable storage according to claim 25, wherein said atleast one code section comprises code for modifying one or more of saidcommunicated signals via at least one of an echo cancellation operation,a near end cross talk (NEXT) cancellation operation, a far end crosstalk (FEXT) cancellation operation, and a forward error correction (FEC)operation.
 32. The machine-readable storage according to claim 25,wherein said at least one code section comprises code for equalizingvideo signals communicated from said video signal source to said videorendering device.
 33. The machine-readable storage according to claim25, wherein said at least one code section comprises code fordistributing an aggregate communication rate evenly or unevenly amongone or more links coupling said video signal source to said videorendering device.
 34. The method according to claim 33, comprising timealigning said communication of said signals among one or more linkscoupling said video signal source to said video rendering device. 35.The machine-readable storage according to claim 33, wherein said atleast one code section comprises code for aggregating a plurality oflinks coupling said video signal source to said video rendering device.36. The method according to claim 25, comprising communicating saidsignals between said video signal source and a plurality of videorendering devices comprising said asymmetric multi-rate Ethernet PHY.